TSMC Unveils Its Strategic Roadmap for the Future

In this article, Gordon directs a series of forward-looking questions to TSMC about where the company is headed next.

Founded in 1987, TSMC pioneered the pure-play foundry model and has since grown into the world’s leading dedicated semiconductor manufacturing partner.

Recently, we posed a number of questions about the company’s next steps. While a TSMC spokesperson declined to address many of them, the responses they did provide still offer valuable insight into where semiconductor technology—and the broader industry—may be heading.

Gordon Feller: As TSMC transitions to process technologies below 2nm, what breakthroughs or obstacles do you expect along the way?

TSMC: The most significant innovation we are introducing at the 2nm node is the nanosheet transistor architecture, also known as gate-all-around (GAA). This is a major milestone: it marks only the second time in our history that we have adopted an entirely new transistor structure, and it is the first such change since the shift from planar transistors to FinFET at the 16nm node in 2014.

After years of technical challenges, TSMC is on track to begin volume production of 2nm technology by the end of this year.

At our A16 node (the 1.6nm-class), we will introduce another major innovation: Super Power Rail, our backside power delivery technology. By dedicating front-side routing resources to signal transmission and moving power routing to the backside, this architecture improves both logic density and performance.

This structure positions A16 as an excellent fit for high-performance computing workloads that require complex signal routing and dense power delivery networks.

GF: Which longer-term technologies—quantum devices, silicon photonics, or alternative materials (such as 2D materials and nanosheet FETs)—are most likely to influence TSMC’s post-2nm strategy?

TSMC: TSMC remains committed to pushing transistor scaling to its limits. However, scaling is not the only path to improving the performance and capabilities of electronic systems.

We are pursuing multiple approaches, including system-level advances enabled by 3D IC, design-technology co-optimization, and the use of innovative materials.

On the scaling front, we have made significant progress in research on complementary FET (CFET) technologies, where transistors are stacked vertically rather than placed on the same plane. In addition, we have conducted extensive research on 2D materials that are only a molecule thick, as well as 1D materials such as carbon nanotubes.

While these materials remain in the research phase and are not yet part of our development roadmap, they show strong potential for addressing future scaling challenges.

Beyond transistors, much of our work focuses on system-level performance—how chips communicate within a system and how they interface with broader platforms. This includes silicon photonics, as well as addressing thermal and power management challenges that arise when multiple chips are integrated into a single package.

Because AI requires processors to access massive volumes of data as quickly as possible, much of our advanced packaging innovation is centered on building larger systems that can integrate more memory and compute.

Today, we already offer wafer-level system technology—single systems as large as a 12-inch wafer—delivering compute capability comparable to a data-center server rack, or even an entire server. At the same time, we are also looking beyond the wafer and exploring larger panel-based system formats.

GF: How does TSMC evaluate the long-term returns of its global fab expansion strategy—particularly in the United States, Japan, and Europe—given rising capital intensity and the expectation of lower learning-curve yields outside Taiwan?

TSMC: Regarding yield learning curves, as our Chairman and CEO Dr. C.C. Wei noted at an investor conference, our first fab in Arizona entered volume production in the fourth quarter of 2024 using N4 technology, and it has achieved yields comparable to our fabs in Taiwan.

Over time, we will continue to leverage expanding scale at the Arizona site and optimize operations to reduce costs. As the site grows, it will benefit from stronger economies of scale and contribute to building a more complete semiconductor supply-chain ecosystem in the United States. We will also continue working closely with customers and suppliers to manage the broader implications.

Our fabs in Europe and Japan are designed to support key technologies for local industries, and their scale will be smaller than our plans in Arizona. Even so, we are confident that we can continue applying the experience we have built both in Taiwan and overseas.

GF: What scenario models is TSMC building around global semiconductor demand driven by AI acceleration—and how might those scenarios shape capacity planning and capital expenditure discipline over the coming decades?

TSMC: We expect AI-related demand to remain strong and continue growing, and we will keep investing in this long-term, demand-driven trend. At the same time, we will stay focused on our fundamentals—technology leadership, manufacturing excellence, and customer trust—to further strengthen our competitive position.

In general, our annual capital expenditures are planned to support growth expectations over the coming years. While the industry experiences short-term cyclical fluctuations, we believe that as long as long-term structural demand and future opportunities remain, we should continue investing.

Our disciplined capex strategy and capacity planning are consistently grounded in long-term market demand forecasts.