How Does a CPU Read and Write Memory?

At first glance, the question of how a CPU reads and writes memory may seem simple, but the reality is far more complex than it appears. The CPU does not act on its own—it only follows instructions generated by the compiler, which translates high-level programming code into machine instructions. In RISC architectures, data cannot be accessed directly from memory; instead, it must first be moved into registers via Load/Store instructions. In contrast, x86 architectures allow direct operations on memory, meaning instructions can fetch data straight from memory or registers. Beyond data, the CPU also constantly fetches the next instruction to execute, since under the von Neumann architecture both data and instructions are stored in memory. This dual need—fetching data and fetching instructions—drives CPU memory access. The challenge lies in speed: CPUs are blazingly fast, while memory lags far behind, creating a massive performance gap. To bridge this gap, engineers turned to cache memory, leveraging the principle of locality—temporal locality (recently used data is likely to be used again) and spatial locality (data near a recently used address is likely to be used soon). Cache, built from SRAM, is much faster than DRAM and sits between CPU and main memory, storing frequently accessed data to prevent constant slow lookups. Even small caches significantly improve performance thanks to locality. However, writing introduces complexity: if the CPU updates cache but not memory, inconsistencies occur. To address this, two strategies are used: write-through (update both cache and memory simultaneously, simple but slow) and write-back (update cache first, then memory later when needed, faster but more complex). Modern CPUs extend this further with multi-level cache hierarchies—L1 (smallest, fastest), L2 (larger, slower), and L3 (even larger but still faster than DRAM). The CPU checks each level before falling back to main memory, balancing speed and cost. Things get more complicated in multi-core systems. Suppose variable X has an initial value of 2. Core C1 caches and updates it to 4, while Core C2 caches its original value (2) and later adds 4, updating its cache and memory to 6. The correct result should be 8, but inconsistency arises because multiple caches hold separate copies. This is solved by cache coherence protocols such as MESI, ensuring updates are synchronized across cores. For programmers, these details matter. Programs with good locality make far better use of caches, while poor patterns cause unnecessary cache misses and performance penalties. In fact, modern CPUs dedicate a large portion of their die area to caches because they are essential for bridging the CPU–memory performance gap. In conclusion, CPU memory access is not a trivial process—it is a carefully orchestrated system of compilers, caches, hierarchies, and coherence protocols, all designed to keep processors running efficiently. Behind every load or store lies a hidden complexity that defines the true performance of modern computing.