The Next Generation of Storage Materials

In recent years, oxide semiconductors have attracted strong interest as promising materials for next-generation memory architectures. Their key advantage lies in enabling logic and memory devices that are compatible with back-end-of-line (BEOL) interconnect processing. This article reviews recent progress and remaining challenges for BEOL memory devices built on oxide-semiconductor channels, including DRAM-like 1T-1C cells, capacitorless gain cells, and non-volatile ferroelectric field-effect transistors (FeFETs).

The discussion highlights the essential properties of oxide channels and focuses on advances in materials and device processing that directly improve core memory metrics such as endurance, data retention, and scalability. Overall, these results offer valuable guidance for optimizing oxide-semiconductor-based memories to meet the demands of emerging applications.

Introduction

The rapid rise of generative AI applications, including large language models (LLMs), is accelerating a shift toward data-centric computing. This transition is driving unprecedented requirements for new memory technologies—higher capacity, greater bandwidth, and better energy efficiency—to sustain increasingly complex workloads.

To address these challenges, oxide-semiconductor (OS) channel materials are emerging as strong candidates for innovative memory cell designs. These approaches are intended to complement conventional memory solutions such as SRAM and DRAM, and to reshape the memory hierarchy by enabling BEOL-compatible architectures. One particularly compelling feature is the ability to implement cell-over-peripheral (COP) designs, made possible by monolithic integration with advanced CMOS logic.

Significant progress has been achieved for n-type oxide semiconductors, including IGZO, InWO, InSnO, and InO. Thanks to ultra-low leakage and compatibility with low-thermal-budget processing below 400 °C, these materials have become natural choices for BEOL memory access transistors. In contrast, identifying p-type oxide channel materials with comparable performance remains far more challenging.

This area remains highly active, and successful pairing of p-type and n-type oxides could unlock opportunities that extend beyond memory systems themselves. Table I summarizes three major categories of BEOL-compatible, oxide-channel-based memory technologies that are currently under intensive study:

1. DRAM-like 1T-1C storage structures using ultra-low-leakage n-type oxide access transistors
2. Capacitorless gain-cell memories composed of n-type and p-type oxide transistors, such as 2T-0C or nT-0C structures
3. Ferroelectric FETs combining an n-type oxide channel with Hf-based ferroelectric dielectrics

In the sections below, we review the latest progress in oxide-semiconductor memory cells and discuss key materials and device challenges that must be addressed to meet performance targets. By examining both n-type and p-type oxide channels, we aim to clarify the factors that most strongly influence device design, scalability, and reliability in emerging memory architectures.

n-Type OS Transistors for DRAM-Like 1T-1C

Recently, a 1T-1C memory chip using n-type oxide-semiconductor transistors was demonstrated on an advanced logic platform, showing a high level of maturity in manufacturing flow and foundry compatibility (Fig. 1a). Operating at VDD = 0.75 V, the chip achieved an 8 ns random cycle time and 128 ms retention time, and demonstrated multi-year-class reliability at 85 °C (Fig. 1b).

The memory array was monolithically integrated above the CMOS periphery using a COP structure. By minimizing signal propagation distance, this approach delivers meaningful benefits in density scaling, latency reduction, and power savings. The strong maturity of n-type oxide semiconductors played a pivotal role in enabling this milestone.

Even so, meeting strict performance and reliability requirements still demands progress on several fronts.

First, in short-channel devices (LG < 30 nm), achieving high on-current (ION) through contact-resistance (RC) optimization is essential to support ultra-low-voltage operation (< 0.75 V) and reduce power.

Second, threshold voltage (VT) must be carefully tuned to suppress leakage while maintaining robust circuit functionality.

Third, process and passivation control must be strengthened to reduce VT variation and improve long-term reliability. Figure 2 summarizes major strategies for n-type OS transistor optimization.

As n-type OS devices continue to scale, lowering RC becomes increasingly critical for boosting ION. Figure 3a compares ID–VG characteristics before and after RC optimization. The improvements include reducing surface damage introduced during contact etching through contact-process engineering, and lowering the metal/semiconductor Schottky barrier height through contact interlayer (IL) optimization. Using these techniques together enabled RC values below 500 Ω·μm (Fig. 3b).

Unlike silicon transistors, VT control and VT-variation management in oxide transistors require fundamentally different levers. This is because performance is governed by a delicate balance among metal-ion concentration, oxygen vacancies, and hydrogen content in the oxide channel. Figure 4 illustrates that precise channel-composition control can provide wide VT tunability. However, these approaches often introduce an undesirable trade-off between VT and ION, reinforcing the need for continued materials and process refinement.

Reliability—especially positive and negative bias temperature instability (PBTI/NBTI)—is highly sensitive to hydrogen in OS transistors. Prior studies show complex PBTI/NBTI behavior in n-type OS systems due to hydrogen diffusion and defect formation. To mitigate these effects, surface treatment and passivation approaches have been used to reduce hydrogen concentration and block hydrogen incorporation during processing, as shown by SIMS depth profiling in Figure 5.

Figure 6 presents endurance results for a 1T-1C memory chip fabricated with an optimized process flow. After 10¹ cycles at 85 °C, the bit error rate (BER) remained below 1 ppm. Figure 7 further shows optimized n-type OS device performance at 25 °C and cumulative distributions of VT and ION across the wafer, confirming strong robustness and low die-to-die variation.

Benchmark results are summarized in Table II, indicating that under the most aggressively scaled gate lengths (LG < 30 nm), the highest ION was achieved while maintaining positive VT operation.

p-Type OS Transistors in 2T-0C Gain Cells

Capacitorless 2T-0C gain cells (GCs), consisting of a write transistor and a read transistor, enable non-destructive readout and represent a highly attractive path toward dense on-chip memory. Oxide-semiconductor gain cells have been validated in both n–n and n–p configurations.

Gain-cell operation is primarily determined by charge stored at the storage node (SN) between the write and read transistors, and is particularly sensitive to capacitive coupling between the write word line (WWL) and the SN. Ultra-low leakage in n-type OS transistors makes them excellent candidates for write devices, since they help retain SN charge during standby.

For the read transistor, p-type channels can be advantageous because weaker capacitive coupling effects can translate into a larger sensing window during readout.

While n-type OS technology is relatively mature, p-type oxide semiconductors remain limited and challenging. In recent years, tin monoxide (SnO) has emerged as a frequently studied p-type oxide candidate due to its favorable thermal compatibility (up to ~350 °C), tolerance to hydrogen, and distinctive electronic structure. In SnO, the valence band is formed through overlap of O-2p and Sn-5s orbitals, supporting p-type transport.

To fully realize SnO’s potential as a gain-cell read transistor, several key issues must still be addressed.

Mobility must be improved and contact resistance reduced to raise on-current.

Hysteresis must be reduced to ensure stable VT.

VT must be made tunable, and ION/IOFF must be increased to suppress leakage and sneak currents—critical requirements for scaling arrays and integrating more cells per bit line.

Earlier proof-of-concept work demonstrated back-gated SnO transistors fabricated by physical vapor deposition (PVD) using lab-scale processes. Typical SnO device ID–VG curves, GI-XRD, and TEM results (Fig. 8a–d) showed strong crystallinity and extracted mobility around 2 cm²/V·s.

Building on that foundation, this article reports updated results for SnO devices fabricated using a foundry-compatible 300 mm wafer process. Figure 9a shows ID–VG behavior for long-channel (LG = 1 μm) SnO devices, achieving ION/IOFF ~ 10 and mobility around 1 cm²/V·s, with hysteresis below 500 mV.

These back-gated devices were fabricated by depositing a metal back gate, then forming a high-κ dielectric via ALD, followed by PVD SnO deposition. After active etch patterning and channel isolation, a SiO interlayer dielectric (ILD) was deposited. Source/drain contacts were then formed through contact etching in the ILD, metal fill, and chemical mechanical polishing (CMP). Notably, these devices also showed strong uniformity across the 300 mm wafer (Fig. 9b).

Even with this progress, additional materials and process optimization is needed to fully unlock SnO device performance.

During PVD SnO deposition, parameters such as oxygen partial pressure (Opp%) and total pressure are crucial for suppressing undesired tin-oxide states (e.g., Sn or SnO₂), which can introduce metallic behavior or unintended n-type transport. Figure 10 shows the VT–ION relationship under different Opp% and total-pressure conditions, indicating strong sensitivity of film quality and device behavior to deposition settings.

The results also suggest that percolation transport may be present in SnO, a phenomenon often observed in n-type oxides as well. Further study is needed to clarify the dominant transport mechanisms in this material system.

For p-type OS transistors, source/drain contact optimization has followed two main directions.

One is reducing interface trap density at the contact/SnO interface, thereby lowering the Schottky barrier height.

The second is increasing local carrier concentration in the source/drain regions to improve band bending and reduce tunneling width.

Figure 11 shows that contact resistance is strongly modulated by gate voltage, consistent with Schottky-contact behavior. With contact optimization, RC was reduced by roughly 5×.

High-Endurance 1T OS-FeFET

Ferroelectric field-effect transistors (FeFETs) using HfZrO (HZO) as the ferroelectric layer are widely considered promising for high-speed, low-power memory due to their electric-field-driven write mechanism. Because both oxide-semiconductor channels and ferroelectric dielectrics can be deposited by ALD, OS-FeFETs offer a realistic path toward dense, cost-scalable 3D memory integration.

However, integrating ferroelectric materials with oxide-semiconductor channels introduces several unique challenges.

One issue is weak erase behavior, driven by insufficient hole carriers in n-type OS channels.

Another is endurance degradation caused by the creation of oxygen vacancies in the oxide channel and their diffusion into the ferroelectric layer.

A major recent breakthrough came from demonstrating a highly scaled OS-FeFET memory device with a cell area of 0.009 μm². Built with an n-type OS channel on a 300 mm wafer, the device achieved 40 μA/μm on-current, 30 ns operation speed, data retention exceeding 1000 s at 85 °C, and endurance up to 10¹² cycles (Fig. 12).

This result was enabled by multiple coordinated engineering strategies.

HZO phase optimization through Zr-content tuning (Fig. 13)

VT control through co-optimization of ferroelectric and OS thickness/composition (Fig. 14)

OS/ferroelectric interface engineering to suppress oxygen-vacancy formation, plus thickness optimization to reduce hard-breakdown risk (Fig. 15)

Doping in HZO to limit oxygen-vacancy diffusion (Fig. 16)

Because OS-FeFETs are non-volatile and driven by electric fields, multi-level-per-bit operation can further increase density. Achieving this at scale, however, will require major improvements in device variability and uniformity to maintain consistent behavior across large arrays.

Conclusion

Oxide-semiconductor-based memory technologies present a compelling opportunity to reshape the memory hierarchy and enable dense, energy-efficient systems that can support the growing demands of data-center-class workloads. Substantial progress has already been demonstrated for novel architectures built on n-type oxide semiconductors.

To fully unlock the broader potential of oxide technology, a critical breakthrough is still needed in p-type oxide semiconductor materials and devices. Success on that front would not only strengthen next-generation memory solutions, but also expand the design space for future BEOL-integrated logic and heterogeneous computing architectures.